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8-String WLED Driver with Integrated Step-Up
Regulator and SMBus/PWM Dimming Capability
Dimming Control Register Descriptions
The MAX17105 includes four registers to monitor and control brightness, fault status, driver ID, and operating mode.
Brightness Control Register: Address is 0x00. This register is both readable and writeable for all 8 bits, and for BRT0,
and BRT7, which are used to control the LED brightness level. In SMBus dimming mode, an SMBus write byte cycle to
register 0x00 sets the output brightness level. The SMBus setting of 0xFF for this register sets the backlight controller to
the maximum brightness output, and 0x00 sets 0.4% backlight brightness. The default value for register 0x00 is 0xFF.
A write byte cycle to register 0x00 has no effect when the backlight controller is in PWM mode. The SMBus read byte
cycle to register 0x00 returns the current brightness level regardless of the dimming mode.
REGISTER 0x00
BRIGHTNESS CONTROL REGISTER
DEFAULT VALUE 0xFF
BRT7
Bit 7 (R/W)
BRT6
Bit 6 (R/W)
BRT5
Bit 5 (R/W)
BRT4
Bit 4 (R/W)
BRT3
Bit 3 (R/W)
BRT2
Bit 2 (R/W)
BRT1
Bit 1 (R/W)
BRT0
Bit 0
(R/W)
Bit Field Definitions:
BIT FIELD
Bit [7:0]
DEFINITION
BRT [7:0]
DESCRIPTION
8-bit brightness setting, adjusting brightness levels in 256 steps, default value is 0xFF.
Device Control Register: Address is 0x01. This register is both readable and writeable for Bit 0 to Bit 2. Bit 0, also
named BL_CTL, is used as on/off control for the output LEDs. Bit 1 and Bit 2, named PWM_SEL and PWM_MD respec-
tively, control the operating mode of the backlight controller. Bit 3 to Bit 7 are reserved bits. All reserved bits, return
0 when read, and are ignored by the controller when written. A value of 1 written to BL_CTL turns on the backlight in
10ms or less after the write cycle completes. A value of 0 written to BL_CTL immediately turns off the backlight.
REGISTER 0x01
DEVICE CONTROL REGISTER
DEFAULT VALUE 0X00
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
PWM_MD
Bit 2 (R/W)
PWM_SEL
Bit 1 (R/W)
BL_CTL
Bit 0 (R/W)
Bit Field Definitions:
BIT FIELD
Bit 2
Bit 1
Bit 0
DEFINITION
PWM_MD
PWM_SEL
BL_CTL
DESCRIPTION
PWM mode select (1 = absolute brightness, 0 = % change) default = 0
Brightness MUX select (1 = PWMI pin, 0 = SMBus value) default = 0
BL on/off (1 = On, 0 = Off) default = 0
The MAX17105 uses two multiplexers internally to direct the dimming signal processing (Figure 4). These two multiplex-
ers are controlled by 2 bits of the device control register, PWM_SEL and PWM_MD, respectively. The PWM_SEL bit
selects either the SMBus or the PWMI input to control the brightness. The PWM_MD bit selects the mode in which the
PWMI input is to be interpreted. Table 4 provides a complete setting of the three dimming modes.
Table 4. Operating Modes Selected by Device Control Register Bits 1 and 2
PWM_MD
X
1
0
PWM_SEL
1
0
0
MODE
PWM mode
SMBus mode
DPST mode
DPWM DUTY-CYCLE SETTING
PWMI input duty cycle
SMBus command
Product of PWMI input duty cycle and SMBus command
X = Don’t care.
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